fix(vt-d): VT-d interrupt remapping initialization with Invalidation Queue support

[ytakano]

Description

VT-d Interrupt Remapping: Initialization with Proper Error Handling

Summary

Initialization of Intel VT-d interrupt remapping with Invalidation Queue support, proper error handling, and spec-compliant GLOBAL_COMMAND register updates.

Changes

Invalidation Queue Implementation

• Completed init_invalidation_queue() function
  • Allocates 4KB DMA page for invalidation queue (256 entries)
  • Configures IQA register with base address and queue size
  • Enables Queued Invalidation via Global Command register
  • Validates register-based invalidation completion before enabling queue

Error Handling Improvements

• Introduced VtdError enum replacing generic error strings

  • IrtpEnableFailed - Interrupt Remapping Table Pointer enable failure
  • IreEnableFailed - Interrupt Remapping enable failure
  • QieEnableFailed - Queued Invalidation enable failure
  • DmaAllocationFailed - DMA memory allocation failure
  • Timeout - Command completion timeout
  • Implements Display trait for human-readable messages

• Updated function signatures to return Result<(), VtdError>

  • init_interrupt_remap() - changed from Result<(), &'static str>
  • set_irta() - changed from () to Result<(), VtdError>
  • init_invalidation_queue() - changed from () to Result<(), VtdError>

Spec-Compliant GLOBAL_COMMAND Updates

• Implemented update_global_command() helper function
  • Follows Intel VT-d 5-step procedure:
    1. Read GLOBAL_STATUS register
    2. Reset one-shot bits (mask 0x96FFFFFF)
    3. Set/clear target bit based on enable flag
    4. Write to GLOBAL_COMMAND register
    5. Poll GLOBAL_STATUS for completion (max 1000 iterations)
  • Enables IRTP, IRE, and QIE individually with proper error propagation

Register-Based Invalidation Completion

• Added a new register definition

  • ICS (offset 0x9c) - Invalidation Completion Status Register

• Implemented wait_register_based_invalidation_complete()

  • Ensures register-based invalidations complete before enabling Queued Invalidation
  • Polls ICS register's IWC bit until clear
  • Prevents race conditions between invalidation mechanisms

Related links

• https://www.google.com/url?sa=t&source=web&rct=j&opi=89978449&url=https://cdrdv2-public.intel.com/671081/vt-directed-io-spec.pdf&ved=2ahUKEwjJ1oCiufaRAxWPnq8BHVbbLy8QFnoECAwQAQ&usg=AOvVaw3fO9wnba58SqsP2HNKwdfu

How was this PR tested?

Tested on an x86_64 machine.

Notes for reviewers